Stephen Pawlowski of Intel gave an interesting keynote today at ISC 2013. He continued the theme of yesterday’s keynote to address challenges our market faces in getting to exascale computing. Here is a summary of the points he made during his talk:
- Getting to exascale by 2020 requires performance improvement of 2x every year
- Innovations anticipated include stacked chips and optical layers
- DRAM is not scaling with Moore’s Law
- More power goes into transferring data than in computing
- Need to operate transistors near threshold
- New materials for DRAM needed. Resistive memory could replace DRAM.
- Need to explore both the big die and the small die paths as we approach 2020
- Big die path leads to 10 billion transistors on a die
- Small die path entails fewer transistors on a small cost effective die
It is clear that Intel is thinking hard about the challenges facing the processor industry and exploring many simultaneous paths to push the market forward.
We look forward to finding the video and slides of Stephen Pawlowski’s keynote posted online, and we’ll provide a link to that information when it is posted by Intel and the ISC 2013 coordinators.
If you are at ISC 2013, you can find us demoing in NVIDIA’s booth #220 near the exhibition entryway.
Bill Dally of NVIDIA gave a wonderful keynote today at ISC 2013. He focused on addressing the challenges facing our market in getting to exascale computing.
He talked about how Moore’s law is alive and well because transistors continue to double at an astonishing rate. However, the additional transistors are not translating into the same big performance gains as they did in the 1990’s. Whereas performance used to grow 50% per year, performance today is growing at a much slower pace.
The biggest bottleneck to more performance is energy efficiency. Bill showed slides of chips and talked about the picojoules required to compute versus those required to move data and operands around the chip. The take home message was that communication across modern processors takes much more power than arithmetic calculations.
In order to get to exascale, we need processors that are 25x more energy efficient than those available today. Only 10% of that performance boost is expected to come from process improvements in silicon technology between now and 2020. The rest will have to come from improvements in circuits and architectures, mainly focused on reducing the power required to communicate data across the chip.
Bill also spent time discussing the software side of HPC. He showed a diagram depicting the interplay between programmers, tool vendors, and architecture teams. He talked about how those 3 groups need to play well together, like kids on a soccer team, in order to move the market forward. Programmers need to rely on tools and focus on their science rather than wasting time re-inventing wheels. Architecture teams need to expose enough interface to the tool developers so that efficient tools can be made. Tools teams need to focus on quality and build trust with programmers.
These are all things we focus on at AccelerEyes with ArrayFire. We spend an enormous amount of manpower in quality testing our software and in working with our users to prioritize features for upcoming ArrayFire releases. Doing so enables us to build useful functions to accelerate science, engineering, and finance codes.
We look forward to finding the video and slides of Bill Dally’s keynote posted online, and we’ll provide a link to that information when it is posted by NVIDIA and the ISC 2013 coordinators.
If you are at ISC 2013, you can find us demoing in NVIDIA’s booth #220 near the exhibition entryway.
